An algorithmic approach to hierarchical parallel optical processing systems

We are currently investigating parallel optoelectronic computing systems based on three dimensional hierarchical architectures[1]. We have previously constructed a system in which two dimensional processing element (PE) arrays are connected by dynamically recon gurable optical interconnections [2]. Current developments in such demonstrator circuits concentrate on improved performance as well as miniaturisation and system packaging issues [3]. Various network topologies can be embedded on such recon gurable hierarchical architectures such that the most appropriate topology is used for any given application. In addition, the 3-dimensional structure enables a cascaded pipelined processing capability. Considering these characteristics, we describe here some important issues in e ciently factorizing algorithms on such optically connected processing systems.